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VHDL: From Simulation to Synthesis: Book by Sudhaker Yalamanchili

VHDL: From Simulation to Synthesis

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ISBN: 9780130809827    Publisher: Pearson Education (US) Year of publishing: 2000     Format:  Paperback No of Pages: 320        Language: English
For courses in Hardware Description Languages, Digital Design Laboratory, Digital Design, and Advanced Digital Design. This text focuses on presenting the basic features of the VHDL language in the context...Read more
For courses in Hardware Description Languages, Digital Design Laboratory, Digital Design, and Advanced Digital Design. This text focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by familiarity with digital logic circuits with simulation and synthesis presented as complementary design processes. Field programmable gate arrays are used as the medium for synthesis laboratory exercises, and tutorials are provided for the use of the new integrated design environments from Xilinx-which is available with the text.
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